1. Field of the Invention
The present invention relates to high density memory devices, and particularly to memory devices in which multiple planes of memory cells are arranged to provide a three-dimensional 3D array.
2. Description of Related Art
3D memory devices have been developed in a variety of configurations that include vertical channel structures. In vertical channel structures, memory cells including charge storage structures are disposed at interface regions between horizontal planes of conductive strips arranged as word lines, string select lines, and ground select lines, and vertical active strips including channels for the memory cells.
A memory device can include multiple blocks of memory cells. Each block can include multiple stacks of horizontal planes of conductive strips arranged as word lines, string select lines, and ground select lines. A defect in a word line in a block can cause the block to fail. When a block fails, it can be marked as a “bad” block and addressed to a good block so the memory device can use the good block instead of the “bad” block. One problem with this method is that a block has a relatively big area so the cost is relatively high.
It is desirable to provide a structure for three-dimensional integrated circuit memory using a vertical channel structure that can provide a word line repair system for the memory at a lower cost.